1. Field of the Invention
The present invention relates to a data transmission line of a semiconductor memory device, and more particularly to a data transmission line of a semiconductor memory device, which can be effectively aligned while optimizing a structure of a repeater connected to the data transmission line.
2. Description of the Prior Art
Recently, as semiconductor devices have been highly integrated, a line width of a circuit is gradually reduced and a line length of the circuit is gradually enlarged.
That is, as high-integration semiconductor memory devices having capacity of 1 G to 4 G have been developed, a data transmission line of a semiconductor device becomes long. For instance, a data transmission line having a length more than 2 cm can be provided for a memory device having capacity above 1 G. Such a long data transmission line may cause an increase of loading capacitance, which is one of resistance factors, thereby significantly lowering a data transmission speed.
FIG. 1 is a schematic view showing an alignment of conventional data transmission lines (GIO_0 to GIO_N). The data transmission lines shown in FIG. 1 may cause signal distortion due to parasitic capacitance created between data transmission lines. In addition, the data transmission speed may be lowered due to a coupling effect generated between neighbor data transmission lines.
In order to solve the above problem, there has been suggested a shielding line, such as a ground line, aligned between data transmission lines. A data transmission line structure including the shielding line can prevent the coupling effect from being generated between data transmission lines, but may cause an increase of load in the data transmission lines so that the data transmission speed becomes lowered.
FIG. 2 is a schematic view showing an alignment of another conventional data transmission lines including a shielding line is aligned between data transmission lines.
As shown in FIG. 2, a shielding line, that is, a ground line is aligned between data transmission lines in order to shield the coupling effect created between data transmission lines. However, the data transmission lines shown in FIG. 2 cannot prevent an increase of load applied to the data transmission lines, so that the data transmission speed may be lowered.
For this reason, there has been suggested an advanced technique employing a repeater for preventing the data transmission speed from being lowered due to an increase of load applied to the transmission lines.
FIG. 3 shows a conventional repeater connected to a data transmission line.
In FIG. 3, GIO_0_L, GIO_0_R, GIO_1_L and GIO_1_R represent data transmission lines used for DDR SDRAM. For instance, GIO_0_L and GIO_0_R represent odd data transmission lines. In addition, GIO_1_L and GIO_1_R represent even data transmission lines.
A control signal (RD_Direction) is enabled during a read operation and a control signal (/RD_Direction) is enabled during a write operation.
If control signal (RD_Direction) is enabled with a high level during the read operation, data of data transmission lines (GIO_0_L and GIO_1_L) are transferred to data transmission lines (GIO_0_R and GIO_1_R) by passing through a repeater including two inverters.
In contrast, control signal (/RD_Direction) is enabled with a high level during the write operation, so that data of data transmission lines (GIO_0_R and GIO_1_R) are transferred to data transmission lines (GIO_0_L and GIO_1_L) by passing through a repeater including two inverters.
FIG. 4 is a schematic view illustrating a structure of a data transmission path of transmission data in a conventional DDR SDRAM employing the repeater as shown in FIG. 3, wherein a data transmission scheme of 4-bit prefetch structure is illustrated.
In FIG. 4, repeaters 401 and 402 include the repeater shown in FIG. 3 as an internal circuit thereof. Repeaters 403 and 404 are identical to the repeater shown in FIG. 3. The repeaters 401, 402, 403 and 404 are connected to a pipe latch unit 410 through data transmission lines (gio_q0_r, gio_q1_r, gio_q2_r, and gio_q3_r). The pipe latch unit 410 includes a plurality of switches 41, 42, 43, and 44. The switches 42 and 44 have a data latch function.
During an operation of the DDR SDRAM, data (DQ0, DQ1, DQ2, and DQ3) transmitted through data transmission lines (gio_q0_l, gio_q1_1, gio_q2_1, and gio_q3_1) connected to the repeater become even data or odd data according to a logic value of column addresses (A<1> and A<0>). Hereinafter, the column address (A<1> and A<0>) is referred to as a “start address”. For reference, data (DQ0, DQ1, DQ2, and DQ3) used in the present invention represent input/output data, which can be continuously inputted/outputted when a burst length is 4.
As generally known in the art, read/write operations of the DDR SDRAM are classified into an even data operation and an odd data operation according to the start address. That is, the data transmission path may vary according to the start address (A<1> and A<0>) of a column address signal applied to the DDR SDRAM from a chip-set. For instance, if the start address (A<1> and A<0>) is “00” or “10”, the even operation is performed. In addition, the odd operation is performed if the start address is “01” or “11”.
In general, the even operation or the odd operation is not specially determined during the write operation for storing data. However, the even operation or the odd operation will be determined according to an address applied from an exterior during the read operation for outputting data.
Conventionally, the even operation or the odd operation is carried out by means of switches 41, 42, 43 and 44 shown in FIG. 4.
Since 4-bit data (DQ0 to DQ3) are applied, the start address is one of “00”, “01”, “10” and “11”.
The switches 41 and 43 determine whether the start address is even or odd. If the start address is odd (that is, “01” or “11”), data (DQ1 and DQ3) are transferred to the switch 42 and data (DQ0 and DQ2) are transferred to the switch 44.
Data transferred to the switch 42 are sequentially outputted while being synchronized with a rising edge of a clock. In FIG. 4, rdo represents output data synchronized with the rising edge of the clock. Data transferred to the switch 44 are sequentially outputted while being synchronized with a falling edge of a clock. In FIG. 4, fdo represents output data synchronized with the falling edge of the clock.
In a case of FIG. 4, the pipe latch unit includes a plurality of internal switches connected to each other in series. Thus, there is a limitation to increase the data transmission speed even if the repeater is provided in the transmission line.
That is, in the next-generation memory device equipped with various internal circuits for controlling data, such as DDR SDRAM, DDR2, and SDRAM, the data transmission speed may be lowered even if the repeater is provided in the transmission line.